INTRODUCTION

The Society of Automotive Engineers (SAE) has adopted a specification known as J1850 “Class B Data Communications Network Interface.” This specification describes two forms of a multiplex bus structure intended for use in a vehicle. The two forms of this multiplex bus are known as Pulse Width Modulation (PWM) and Variable Pulse Width (VPW). The AVT-921 Dual Interface implements both versions of the J1850 standard (simultaneous operations are not permitted).

The AVT-921 Dual Interface provides the following functions:

• Isolated electrical interface between the subject vehicle and the host computer.
• Protocol/data conversion between the vehicle J1850 multiplex bus and the host computer via the ISA bus.
• Passive network traffic monitor.

When in VPW mode of operation the AVT-921 permits both transmit and receive operations at 4 times the normal speed (4X mode). This mode of operation is not supported by the J1850 specification. 4X mode may be required to be compatible with General Motors’ Class 2 system.

Installation and Connections

Connecting the AVT-921 to the subject vehicle is easily accomplished via an OBD-II compatible cable (available separately). One end of the cable mates with the DA-15 connector on the AVT-921. The other end mates to the vehicle OBD-II connector. No other connections are required. The cable may be connected or disconnected at will without affecting the host computer.

No other connections or installation is required.

Hardware Configuration

Specifications and Requirements

Host Computer:
• PC-AT compatible computer.
• One 8-bit ISA slot.
AVT-921 Dual Interface Board:
• Overall size: 4.2 high x 10.0 inches long
(XT form factor, 3/4 length)
• Weight: 7 oz.
• +5 VDC from host computer.
• +12 volts from either host computer or the subject vehicle.
(The two sources are diode isolated.)
• Power dissipation: 1.5 watts (nominal).

AVT-921 Hardware

A block diagram of the AVT-921 Dual Interface board is shown in Figure 1. The heart of the unit is the HIP7030A0 microcontroller. This device utilizes a 68HC05 core with a bus speed of 5 MHz. The operational firmware is contained in an EPROM that is organized into two code sections. One code section is for VPW operations only while the other code section is for PWM operations only.

Other AVT-921 functional blocks include two FIFO’s, a PWM interface, a VPW interface, a bus multiplexer, electrical isolation of the host computer from the vehicle, and two hardware control/status registers. VPW mode operations utilize the Motorola MC68HC57 Data Link Controller (DLC-S) which includes the VPW bus transceiver function. PWM mode operations utilize the Motorola HBCC device and a Ford Motor Company PWM bus transceiver design.

The two FIFO’s on the AVT-921 are configured as a set of bi-directional mail boxes for message passing between the microcontroller and the host computer. Each FIFO is 4 KBytes deep and fully asynchronous. They facilitate communications between the host and the microcontroller while minimizing the risk of lost data and eliminating the requirement for real-time response from the host.

The electrical isolation barrier is depicted on the block diagram. The AVT-921 Dual Interface derives its operating power (+5 VDC and +12 VDC) from the host computer. Additionally, a connection exists between the AVT-921 and the subject vehicle unswitched battery positive (V_BATT). This supply is diode isolated and electrically isolated from the host +12 VDC supply. This arrangement permits
normal AVT-921 operations even when not connected to a subject vehicle. When the AVT-921 is connected to a vehicle the V_BATT connection provides a common positive supply for all network nodes.

Selecting the mode of operation for the AVT-921 is accomplished through software commands on the host computer. These commands result in writing appropriate values (via the ISA bus) into hardware control register #2 on the AVT-921 board. Bits in this register control the reset line, memory paging, and other functions.

AVT-921 Operation

The AVT-921 is mapped into the memory space (not I/O space) of the host computer. The base address of the AVT-921 board is determined by the setting of two 8-bit DIP switches. All communications between the host and the AVT-921 are via the ISA bus.

The structure and protocol of communications between the AVT-921 and the host computer are such that all data is transferred in packets. The size of each data packet varies from 1 byte to 16 bytes (inclusive). The first byte in each data packet is the header byte and is used to convey information only between the AVT-921 Dual Interface board and the host computer.

The header byte is divided into the upper nibble and lower nibble. The upper nibble indicates what information the data packet is conveying. The lower nibble is the count of the number of bytes that follow the header byte. The meaning of the upper nibble of the header byte depends on which direction the data packet is moving; whether to or from the host computer.

Messages from the host computer to the AVT-921 are known as Commands. Messages from the AVT-921 to the host computer are known as Responses. The following are excerpts from the User’s Manual. Please consult the latest revision manual for up-to-date information.

ISA Bus Memory Map

The AVT-921 Dual J1850 Interface board is a memory mapped device and is accessed via memory operations through the ISA bus. The base or segment address of the board is determined by the setting of DIP switches on the board. The board occupies 16 bytes of memory space, only 3 bytes are actually used. Accessible via the ISA bus are Hardware Register #2, FIFO #1, and FIFO #2. The address of each of these functions is listed relative to the base address of the board. All unused addresses are not accessible and are not listed.
Address: $00 Hardware Register #2 (read/write)
Address: $01 FIFO #1 (write only)
Address: $02 FIFO #2 (read only)

Figure 1 AVT-921 Unit Block Diagram

Command Header Byte

This byte is prepended onto a packet transmitted by the control computer to the AVT-921 Dual Interface board.
Low nibble, bits b3 - b0: Byte count (how many bytes to follow); may be zero when the message is only a status or error message.
High nibble, bits b7 - b4 (undefined or reserved values are not listed):

$0x: This is a valid packet for transmission. (The null byte, $00, is ignored.)
$1x: This is a valid packet for IFR transmission. (Not currently implemented.)
$2x: Reset command, must be followed by a byte specifying the device to be reset.
{$21 $01: Reset the HBCC device.}
{$21 $03: Reset the DLC-S device.}
{$21 $04: Reset FIFO #1.}
{$21 $05: Reset FIFO #2.}
$7x: HIP7030A0 write RAM (address byte, data byte, follow).
$8x: HIP7030A0 read RAM (address byte, requested bytes [<=$0E], follow).
$9x: Hardware Register #1 write (data byte follows).
$Ax: Hardware Register #1 read.
$Bx: Request firmware version number.
$Cx: 4x mode command. ($C0: request status; $C1 $00: Off; $C1 $01: On).
$Dx: Request operational mode.
$Fx: Hardware unit Re-Start command, must be followed by $A5. [$F1 $A5]

This byte is prepended onto a packet transmitted by the AVT-921 Dual Interface board to the control computer.
Low nibble, bits b3 - b0: Byte count (how many bytes to follow); may be zero when the message is only a status or error message.
High nibble, bits b7 - b4 (undefined or reserved values are not listed):

$0x: This is a valid packet received from the bus.
$2x: Error message, error byte(s) follow.
$3x: Command message error, error header byte follows.
$7x: HIP7030A0 read RAM error, requested byte count greater than $0E.
$8x: HIP7030A0 read RAM (address byte, data bytes, follow).
$9x: Board status information byte follows:
{$21 $03: HBCC initializations complete.}
{$21 $04: Firmware version number follows.}
{$21 $06: PWM operation (Motorola).}
{$21 $07: VPW operation (Motorola).}
{$21 $08: DLC-S initializations complete.}
$Ax: Message status information. ($A1 $10 arbitration lost, message flushed.)
$Bx: Transmit message too long (> 11).
$Cx: 4x mode status response. ($C1 $00: Off; $C1 $01: On).
$Dx: Hardware Register #1 read, data byte follows.

The received message status byte always follows the header byte, even if the status byte is the result of transmitting a message.

Bit Definition
0: CRC error.
1: Incomplete message (incorrect number of bits).
2: Break received.
3: IFR data.
4: Lost arbitration.
5: Transmission successful.
6: From this device.
7: Bad message.

Example #1: Want to request the current operational mode.

Command: D0.

Explanation: The HIU will respond with: 91 07. The ‘9’ indicates a board response, the ‘1’ indicates one byte follows, and the 07 indicates VPW mode (using the DLC-S device).

Example #2: Want to send a message out on the bus.

Command: 04 32 89 AC 5F.

The 04 indicates the packet is destined for the bus, as a message, with four bytes to follow. The AVT-921 will respond with: 01 60. The ‘0’ indicates a received message and the ‘1’ indicates only one byte, which is the received message status byte. The ‘60’ indicates that bits 6 and 5 are set which means the received message was from this device and the transmission was successful. (Messages transmitted by the AVT-921 are received by the AVT-921, are checked, but are not echoed back to the controller. Only a status byte is passed to the controller to indicate the status of the transmitted message.)

Company Overview

The engineering staff at AVT, Inc. has combined experience on a number of multiplex bus standards including: J1850 VPW and PWM and ISO-9141 and 9141-2. Members of the staff are available to provide assistance on the use of any of AVT’s products.

AVT engineering staff members are available to provide dedicated engineering support for a customer project. Through a simple contractual arrangement, a customer is able to ‘tap’ into AVT’s knowledge and experience base.

Information on any of the products or engineering support that Advanced Vehicle Technologies can provide is available by calling, faxing, or writing.